In recent years, electronic devices such as a cellar phone, a notebook-size personal computer, PDA and a digital video camera have been increasingly used, and they are becoming smaller, thinner and lighter. There has been also increasing a demand for a high performance and a multifunction of the electronic devices. As a result, electronic components such as a semiconductor device and a circuit component are becoming ultrasmall, and thereby a mounting process or a packaging process of the electronic components has been improved. Also, a high-density process of an electronic circuit has been rapidly improved.
The technology needed for the high-density process of the electronic circuit is a high-density mounting technology or a high-density packaging technology for a semiconductor integrated circuit (LSI). With a rapid development of a high pin-number and a fine pitch for connecting electrodes (which are hereinafter referred to also as “electrode(s)”) of a LSI chip, semiconductor packaging technologies such as CSP (chip size package) by performance of the flip chip mounting of a bare chip as well as PPGA and BGA mounting processes for external terminals have been commonly used. Therefore, there is a demand for a new mounting technology or a new packing technology that can accommodate a high-speed processing and a miniaturization of a mounted IC as well as a high number of input/output terminals of the mounted IC.
In a flip chip mounting process, firstly, a plurality of electrode pads are formed on a semiconductor chip. Then, bumps are formed on the electrode pads by using a material such as a solder, Au or the like. Subsequently the semiconductor chip is mounted over a circuit substrate such that the bumps of the semiconductor chip are opposed to a plurality of electrodes formed on the circuit substrate. This results in a formation of an electrical conduction between the bumps and the electrodes. After that, a resin material (underfill agent) is poured into a clearance gap between the semiconductor chip and the circuit substrate so as to form a mechanical connection between the semiconductor chip and the circuit substrate.
For mounting a next-generation LSI having 5000 or more electrodes over a circuit substrate, it is required to form fine-pitch bumps with their pitch of 100 μm or less. It is, however, difficult for a conventional solder bump-forming process to form such fine-pitch bumps.
Moreover, from a viewpoint that a large number of bumps must be formed according to the number of the electrodes, a high productivity is required for reducing a manufacturing cost by reducing mounting tact time per chip.
There has been developed a plating process and a screen printing process as a conventional bump-forming process. The plating process is suitable for achieving a fine pitch, but it is complicated and has to compromise the productivity. The screen printing process, on the other hand, has a high productivity, but is not suitable for achieving the fine pitch since a mask is used.
Recently, there has been proposed several processes for selectively forming solder bumps on electrodes of a LSI chip or a circuit substrate. These processes are not only suitable for a fine chip of the bumps, but also suitable for achieving a high productivity since a plurality of the fine bumps can be formed in a batch process. Accordingly they are expected as promising processes that can be applicable to a mounting or packaging for the next-generation LSI.
According to one of these promising processes, a solder paste comprising a mixture of solder powder and a flux is applied directly onto a whole surface of a circuit substrate having electrodes (surfaces of the electrodes have been oxidized). Subsequently the circuit substrate is heated so as to melt the solder powder. As a result, solder bumps (solder layers) are selectively formed on the electrodes without causing an electrical short circuit between the adjacent electrodes. See Japanese Patent Kokai Publication No. 2000-94179 (which is referred to also as “Patent literature 1”), for example.
According to another one of the promising processes, a paste composition (so-called “deposition type solder using chemical reaction”) mainly comprising organic acid lead salt and tin metal is applied onto a whole surface of a circuit substrate, the surface being provided with electrodes. Subsequently the circuit substrate is heated so as to induce a displacement reaction for Pb and Sn, and thereby Pb/Sn alloy is selectively deposited on the electrodes of the circuit substrate. See Japanese Patent Kokai Publication No. H01-157796 (which is referred to also as “Patent literature 2”) and “Electronics Packaging Technology”, issued on September, 2000, pp. 38-45 (which is referred to also as “Non-patent literature 1”), for example.
There is also another process wherein bumps are selectively formed on electrodes of a circuit substrate. In this process, the circuit substrate is immersed in a chemical solution so as to form an adhesive film only on surfaces of the electrodes of the circuit substrate. Then, solder powder is put into contact with the adhesive film so as to attach the solder powder to the electrodes. See Japanese Patent Kokai Publication No. H07-74459 (which is referred to also as “Patent literature 3”), for example.
However, when the above-mentioned processes are employed, the flip chip mounting process requires the following steps (1) and (2) due to the fact that the bumps are formed on the electrode pads of the semiconductor chip or on the electrodes of the circuit substrate:
(1) The step for forming an electrical connection between the opposed electrodes by performance of a reflow process after the formation of the bumps and the mounting of the semiconductor chip over the circuit substrate; and
(2) The step for pouring an underfill resin into a clearance gap formed between the semiconductor chip and the circuit substrate so as to secure the semiconductor chip to the circuit substrate.
The steps (1) and (2) will cause an increase of the manufacturing cost.
Therefore, there is recently proposed another process. According to such process, an electrical connection is formed at desired position by disposing a film consisting of an anisotropic conductive material (which contains electrically-conductive particles) between a projected electrode of a semiconductor chip and an electrode of a circuit substrate, followed by heating and pressurizing the film. See Japanese Patent Kokai Publication No. 2000-332055 (which is referred to also as “Patent literature 4”), for example.
There is also proposed another process wherein an electrically-conductive adhesive consisting of a thermosetting resin and electrically-conductive particles is supplied between a semiconductor chip and a circuit substrate, and thereafter the semiconductor chip is pressurized and the electrically-conductive adhesive is heated. According to this process, the molten electrically-conductive particles are allowed to gather between electrodes of the semiconductor chip and electrodes of the circuit substrate. As a result, an electrical conduction between each electrode of the semiconductor chip and each electrode of the circuit substrate is formed, and also a bonding between the semiconductor chip and the circuit substrate is formed. See Japanese Patent Kokai Publication No. 2004-260131 (which is hereinafter referred to also as “Patent literature 5”), for example.